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Sudeb Dasgupta
Sudeb Dasgupta Associate Professor sudebfec[at]iitr.ac.in +91-1332-285666 Website
Areas of Interest
  • Ultra Low Power, Adiabatic Logic for Portable Applications
  • Low Power Application, Subthreshold Logic Design
  • Radiation Effects on ICs, Design and Development of 6T FinFET Based Rad Hard SRAM Cell
  • Novel Semiconductor Devices, FinFETs, PDSOI, FDSOI
  • Nanoelectronics, Semiconductor Device Modelling
Professional Background
FromToDesignationOrganisation
20052006Assistant ProfessorIndian School of Mines, Dhanbad
2006On GoingAssistant ProfessorIndian Institute of Technology, Roorkee
20002005LecturerIndian School of Mines, Dhanbad
2006On GoingReviewerIEEE Transactions on Nanotechnology
2003On GoingReviewerVLSI Design and Test Symposium
2003-1965ReviewerSemiconductor Science and Technology IOP
2004-1965ReviewerIETE J. of Research
2006-1965ReviewerInternational Journal of Electronics TAF
2004On GoingReviewerInternational VLSI Design Conference
19982000Technical Committee MemberVISION-2000
2007-1965ReviewerIEEE Transactions on VLSI
2004On GoingReviewerInternational VLSI Design Conference
Honors and Awards
AwardInstituteYear
Expert MemberThe Global Open University, The Netherlands2001
Senior REsearch FellowDepartment of Science and Technology, GOI1997
Marquis's Who's Who in Science in Engineering, USAMarquis2006
Best Paper AwardIWPSD-20052005
Technical Commitee MemberInternational Conference on Micro-to-Nano2006
Erasmus Mundus FellowPolitechnico di torino2010
IUSSTF FellowUniversity of Wisconsin, Madison, USA2011
DAAD FellowTU, Dresden, Deutschland2013
Educational Details
DegreeSubjectUniversityYear
Ph.DElectronics EngineeringBanaras Hindu University2000
Administrative Background
FromToDesignationOrganisationLevel
20061965O.C. PurchaseIIT Roorkee
20152017Chairman, DAPCIIT Roorkee
20062011O.C. VLSI Design LabIIT Roorkee
20052005Member, Institute Web-site CommitteeIndian School of Mines, Dhanbad
20022005Member, time-Table CommiteeIndian School of Mines, Dhanbad
20032005Member, Departmental Research CommiteeIndian School of Mines, Dhanbad
20032004Member Secretary, Board of Courses and StudiesIndian School of Mines, Dhanbad
20002005Member, Tender Adisory CommitteeIndian School of Mines, Dhanbad
2006On GoingCo-CoordinatorIIT-R SMDP For VLSI Design and Related S/W - Phase-II
2006On GoingO.C.Solid State Devices (R&D) Lab
2007On GoingMemberDUGC, E&CE
20012003WardenIndian School of Mines, Dhanbad
20032005Member, Research CouncilIndian School of Mines, Dhanbad
20022003Member, Academic CouncilIndian School of Mines, Dhanbad
Sponsored Research Projects
TopicFunding AgencyYear
Modelling and Simulation of Nanoscale MOSFET for their use in future VLSI/ULSI schemesMinistry of Human Resources and Development, GOI2003
SMDP-C2SDEITY2015
SMDP-II, http://192.168.121.8/departments/ECE/uploads/File/smdp/index.htmlMinistry of Information and Communication Technology, Government of india2005
Memberships
  • EDS, Member
  • ISTE, Member
  • Institute of Nanotechnology, Associate Member
  • IEEE, Member
Teaching Engagements
TitleCourse CodeClass NameSemester
digital ElectronicsEC-203B.Tech-II EC& CSEAutumn
Electronic Network TheoryEC-291B.Tech II YearSpring
Lab-IIEC-650P.G.(including Pre Phd Course)Spring
Semiconductor Device Models for Circuit SimulationEC-502P.G.(including Pre Phd Course)Autumn
Semiconductor Device LabEC-550P.G.(including Pre Phd Course)Autumn
Analog VLSI DesignEC-558P.G.(including Pre Phd Course)Autumn
Semiconductor LABEC-351U.G.Autumn
Digital VLSI DesignEC-557P.G.(including Pre Phd Course)Spring
VLSI TechnologyEC-555P.G.(including Pre Phd Course)Spring
Projects and Thesis Supervised
Title of ProjectNames of Students
DESIGN OF LOW POWER DIGITAL FILTERKshipra Jain, Sonal Tyagi and Sujit Kumar
A CMOS Phase Frequency Detector for High Speed PLL with Linear Phase Transfer CharacteristicsMohammed Khadar
Compact Analytical Modelling of Gate Leakage Current with S/D overlap for Nanoscale N-MOSFETAshwani Rana
Designing of ALU for a 16-bit RISC Microprocessor Architecture Avnish Varshney
Research Scholar Groups
Scholar NameInterest
Annada SarabModeling and Simulation of Quantum Effect in Nanoscale MOSFET
Balwinder RajFinFet Device Modeling and Nanoscale Memory Design
V. RameshLow Power VLSI Design
Surendra RathodStudy of Radiation Effects on SOI based devices and circuit
Jitendra KanungoAdiabatic Logic Design
Ashutosh NandiDual-k FinFET based Analog Design
Pankaj PalSRAM memory design enhancements using sub 22 nm devices
PHDs Supervised
TopicScholar NameStatus of PHDRegistration Year
Modelling and Simulation of Nanoscale Metal Oxide Semiconductor Feild Effect TransistorsA. Annada Prasad SarabA1
Analytical Modeling of Nanoscale MGDG MOSFET and its Application to SRAMS. K. VishvakarmaA1
Analytical Modeling of Double Gate FinFET and its Applications to SRAM Cell DesignBalwinder RajA1
Sub threshold Logic Design for Low Power ApplicationsRamesh VaddiA1
Radiation Effect on SOI based devices and circuitsSurendra RathodA1
Adiabatic CircuitsJitendra KanungoA1
Silicon NanowiresGaurav KaushalA1
FinFET Design IssuesAshutosh NandiO1
Robust Nanoscale Circuit StudiesNaushad AlamA1
Variability studies in decanano FiNFET based circuits and systemsMenkaO1
FinFETs for RF ApplicationsSavitesh SharmaO1
Visits to outside institutions
Institute VisitedPurpose of VisitDate
UNIK, NorwayJoint Research15-07-2009
Politechnico Di Torini, ItalyResearch, EM Fellow20-05-2010
University of Wisconsin-MadisonIndo US Fellowships, Collaborative Research20-05-2011
Participation in short term courses
Couse NameSponsored ByDate
Instruction Enhancement ProgrammeIIT-Kanpur/ SMDP-II03.07.2006
Courses or Conferences Organised
Conference NameSponsored ByDate
STEP-VHDLSTEP/IITR
Refereed Journal Papers
Semi-numerical Modelling of an n-channel Irradiated MOSFET
By: S.Dasgupta and P.Chakrabarti
Published in: International Journal of Electronics Vol: 88 (Pg 301-313) Date: 2001
Influence of Ionising Radiation on CMOS Inverters
By: S.Dasgupta, R.K. Chauhan and P. Chakrabarti
Published in: Microelectronics Journal (Elsevier) Vol: 32 (Pg 615-620) Date: 2001
Ionising Radiation effects in an Ion-Implanted MOSFET: A Two-Dimensional Analytical Study
By: S.Dasgupta, R.K. chauhan, G. Singh and P. Chakrabarti
Published in: International Journal of Electronics Vol: 89 (Pg 277-288) Date: 2002
A pseudo-two-dimensional model of an n-channel MOSFET under the influence of Ionising Radiation
By: S.Dasgupta, R.K. Chauhan and P. Chakrabarti
Published in: Semiconductor Science and Technology (IOP) Vol: 17 (Pg 961-968) Date: 2002
Two-Dimensional Numerical Modeling of a deep sub-micron Irradiated MOSFET to extract its Global Char
By: S.Dasgupta
Published in: Semiconductor Sceince and Technology (IOP) Vol: 18 (Pg 124-132) Date: 2003
Self-consistent Solution of Two-dimensional Poisson Equation and Schrodinger Wave Equation for Nano-
By: Deepesh Jain and S.Dasgupta
Published in: Journal of Nanoscience and Nanotechnology (APS) Date: 2004
Two-dimensional numerical modeling of lightly doped nano-scale double-gate MOSFET
By: Deepanjan Datta, A.A.P.Sarab and S.Dasgupta
Published in: Journal of Computational and Theoretical Nanoscience Vol: 3 (Pg 414-422) Date: 2005
Study of the Leakage Current in Novel Nanoscale Device Architecture depending on Doping Profile
By: D.Datta and S.Dasgupta
Published in: Journal of Computational and Theoretical Nanoscience Vol: In press Date: 2006
Self-Consistent Solutions of 2D-Poisson and Schrodinger Wave Equations for a Gaussian Doped 50 nm MO
By: A. Agrawal and S.Dasgupta
Published in: Journal of Computational and Theoretical Nanoscience Vol: 3 (Pg 101-109) Date: 2006
Design and Development of Ultra Low Power MOS based VLSI Architecture
By: Deepanjan Datta and S.Dasgupta
Published in: Journal of Computational and Teoretical Nanoscience (APSBS) Vol: 3 (Pg 01-11) Date: 2006
Two-Dimensional Analytical Modeling of Gaussian Doped Nano-scale Double-gate MOSFET
By: D.Datta, A.A.P.Sarab and S.Dasgupta
Published in: Microelectronics Journal (Elsevier) Vol: 37 (Pg 537-545) Date: 2006 (online)
Nanoscale Device Architecture to Reduce Leakage Current through QM Modelling Schemes in current VLSI Technology Node
By: A.A.P.Sarab, Deepanjan Datta and S.Dasgupta
Published in: Virtual Journal of Nanoscale Science and Technology Vol: 00 (Pg 1384-1397) Date: 2006
Novel Design Technique to reduce off state power dissipation in MOS based devices: A QM Study
By: Deepanjan Datta, Samiran Gangulay, A.A.P.Sarab and S.Dasgupta
Published in: Journal of Vacuum Science and Technology-B Vol: 24 (Pg 1384-1397) Date: 2006
Novel Nanoscale Device architecture to reduce Leakage Currents in Logic Circuits: A Quantum-Mechanic
By: D.Datta, S. Ganguly, A.A.P.Sarab and S.Dasgupta
Published in: Semiconductor Science and Technology (IOP) Vol: 21 (Pg 397-408) Date: 2006
Modeling and Simulation of the Nanoscale Triple-Gate
By: Deepanjan Dutta, A.A.P.Sarab and S.Dasgupta
Published in: Journal of Nanoscience and Optoelectronics Vol: 01 (Pg 1-14) Date: 2006
Low Band-to-Band Tunnelling and Gate Tunnelling Current in Novel Nanoscale Double-Gate Architecture: Simulations and Investigation
By: Deepanjan Dutta, samiran Ganguly and S.Dasgupta
Published in: Nanotechnology (IOP) Vol: 18 (Pg -) Date: 2007
Analytic Modeling of Non-Uniform Graded Dopant Profile of Polysilicon Gate in Gate Tunelling Current for N-MOSFET in Nanoscale Regime
By: Ashwani Kumar and S.Dasgupta
Published in: Journal of Computational and Theoretical Nanoscience Vol: 4 (Pg 179-185) Date: 2007
Unified Compact Modelling of a Gate Tunneling current considering Image Forge Barrier Lowering for nanoscale N-MOSFET
By: Ashwani Kumar and S.Dasgupta
Published in: Journal of Computational and Theoretical Nanoscience Vol: 4 (Pg 482-487) Date: 2007
Analysis and Evaluation of Output characteristics of Gaussian doped Nanoscale MOSFET using Green's
By: Ritambhar Roy and S.Dasgupta
Published in: Journal of Computational and Theoretical Nanoscience Vol: 3 (Pg 811-817) Date: 2006
Quantum Mechanical Treatment for the reduction of various leakage components in novel nanocscale MOS
By: Deepanjan Datta, A.A.P.Sarab and s.Dasgupta
Published in: Journal of Nanoscience and Optoelectronics Vol: 01 (Pg 237-250) Date: 2006
Evaluation of Threshold Voltage for 30 nm Symmetric Double Gate (SDG) MOSFET and it’s Variation with Process Parameters
By: S. K. Vishvakarma, B. Raj, A. K. Saxena, Rahul Singh, Chinmaya R. Panda and S. Dasgupta
Published in: Journal of Computational and Theoretical Nanosciences , American Scientific Publishers (ASP) Vol: in press (Pg Accepted) Date: 0/0/0000
Two Dimensional Analytical Potential Modeling of Nanoscale Symmetric Double Gate (SDG) MOSFET with Ultra Thin Body (UTB)
By: S. K. Vishvakarma, Vinit Agrawal, B. Raj, S. Dasgupta, A. K. Saxena
Published in: Journal of Computational and Theoretical Nanoscience Vol: 4 (Pg 1144-1148) Date: Sept. 2007
Modeling of Inversion Charge Density in Nanoscale Symmetric Double Gate (SDG) MOSFET: An analytical Approach
By: S. K. Vishvakarma, B. Raj, A. K. Saxena and S. Dasgupta
Published in: Journal of Nanoelectronics and Optoelectronics, American Scientific Publishers (ASP) Vol: 2 (Pg in press) Date: 2007