Title: From theory to practice: the Marvellous journey of Mighty MPC

Abstract: Secure Multi-party Computation (MPC) is the standard-bearer and holy-grail problem in Cryptography that permits a collection of data-owners to compute a collaborative result, without any of them gaining any knowledge about the data provided by the other, except what is derivable from the result of the computation. The area was introduced in the seminal work of Yao in 1982. Since then the theory of MPC has seen some of the most fundamental results in theory of computation. Technology follows techniques and so a huge effort has gone in for turning techniques of MPC to technology. In this talk, I plan to cover the contribution we made towards solving real-world problems via applied MPC. The broad domains we tackle include social good, Health, FinTech and Smart cities.

Bio: Arpita Patra is presently an Associate Professor at Indian Institute of Science and a visiting faculty researcher at Google Research. Her area of interest is Cryptography, focusing on theoretical and practical aspects of secure multiparty computation protocols.
She received her PhD from Indian Institute of Technology (IIT), Madras and held post-doctoral positions at University of Bristol, UK, ETH Zurich, Switzerland, and Aarhus University, Denmark.
Her research has been recognized with Google Privacy Research Faculty Award 2023, J P Morgan Chase Faculty Award 2022, SONY Faculty Innovation Award 2021, Google Research Award 2020, NASI Young Scientist Platinum Jubilee Award 2018, SERB Women Excellence award 2016, INAE Young Engineer award 2016 and associateships with various scientific bodies such as Indian Academy of Sciences (IAS), National Academy of Engineering (INAE ), The World Academy of Sciences (TWAS). She is a council member of Indian Association for Research in Computing Science (IARCS).
She has coauthored a textbook on Multi-party Computation titled “Secure Multiparty Computation against Passive Adversaries”.

More about her research is available here

Title: Fast, Furious and Insecure: Passive Keyless Entry and Start Systems in Modern Supercars

Abstract: In this talk we will summarize three real-world security analyses of PKES systems. We begin with the PKES system used in Tesla Model S (prior to our responsible disclosure). We reverse engineered the system and discovered several security weaknesses, which allow us to clone a key fob in a matter of seconds. Next we look at the same system after Tesla deployed a security fix in response to our findings. We discovered a vulnerability which allows to still clone a key fob with twice the effort compared to the initial attack. We close with the PKES system used in Tesla Model X. This system employs secure symmetric-key and public-key cryptographic primitives implemented by a Common Criteria certified Secure Element. We reverse engineered the system and discovered several issues which allow us to bypass all of the cryptographic security measures put in place. We developed an attack which enables us to gain access to the vehicle's interior in a matter of minutes and pair a modified key fob, allowing to drive off. Besides the security analyses we will also briefly report on our responsible disclosure efforts. Finally, our work highlights how hard it is to deploy seemingly simple cryptographic solutions in increasingly complex and connected vehicular systems.

Bio: Dr Benedikt Gierlichs is a research expert in the COSIC (Computer Security and Industrial Cryptography) research group at KU Leuven in Belgium. He works with the embedded security sub-group and leads the attacks and evaluations team. His research focuses on the (physical) security of embedded devices. He enjoys to apply cryptography to solve complex real-world challenges. He has co-authored more than 70 scientific publications in peer-reviewed, international conferences and journals. He has served on many program committees of international conferences and has co-chaired 4 of them. He is a member of the IACR, a Belgian delegate to the ISO/IEC SC27 standardization group and chairman of the CHES steering committee.

His research interest include Physical security of embedded cryptographic devices, Side Channel Analysis, Fault Analysis, Countermeasures, Secure system on chip design
More about his reserach is available here

Title: Side-channel analysis of post-quantum cryptographic algorithms.

Abstract: Side-channel attacks are one of the most efficient physical attacks on implementations of cryptographic algorithms at present.
They exploit the correlation between physical measurements (power consumption, electromagnetic emissions, timing) taken at different points during the algorithm's execution and the secret key.
In this talk, we will present our recent side-channel attacks on implementations post-quantum cryptographic algorithms, including profiled deep learning-based power analysis of a higher-order masked implementation of CRYSTALS-Kyber key encapsulation mechanism.
Last year CRYSTALS-Kyber has been selected for standardization by the NIST and included in the NSA suite of cryptographic algorithms recommended for national security systems.

Bio: Elena Dubrova received the Diploma Engineer degree in Computer Science from Technical University of Sofia, Bulgaria, in 1993, and Ph.D. degree in Computer Science from University of Victoria, B.C., Canada, in 1998.
Since 2008 she has been a professor at the School of Electrical Engineering and Computer Science at the Royal Institute of Technology, Stockholm, Sweden.
She has over 100 publications and 15 granted patents.
Her work has been awarded prestigious prices such as IBM faculty partnership award for outstanding contributions to IBM research and development.
She is a world's top 2% scientist according to the Stanford University ranking from 2020. Her research interests include hardware security, lightweight cryptography, logic synthesis, and multiple-valued logic.

Title: On designing Social Norm-Grounded Privacy preserving Systems

Abstract: Today, data privacy (collection, storage, sharing, and processing of personal data) is often highlighted in public discourse with the advent of a multitude of recent government-mandated privacy regulations like GDPR and CCPA. To that end, in this talk, I will discuss our current and ongoing body of work on creating social norm-grounded privacy-preserving systems-—systems that help to align the collection, sharing, or storage of large-scale personal user data in online systems with rules collectively created by groups of users in particular and society in general. I will give an overview of our work in this space and focus on a few specific use cases from our ongoing research in this space. I will conclude this talk by touching on our general research agenda of understanding, designing, and building human-in-the-loop, private, secure, and abuse-free systems.

Bio: Mainack Mondal is an Assistant Professor at Department of Computer Science and Engineering, IIT Kharagpur, India.
He completed his Ph.D. from the Max Planck Institute for Software Systems (MPI-SWS), Germany, in 2017.
Prior to joining IIT Kharagpur, he was a postdoctoral researcher at the University of Chicago and Cornell Tech.
Mainack is broadly interested in incorporating human factors into security and privacy and consequently designing usable online services.
Specifically, he works on developing systems that provide usable privacy and security mechanisms to online users while minimizing system abuse.
His work has led to papers in Usenix Security, ACM's CCS, NDSS, AsiaCCS, PETS, AAAI's ICWSM, Usenix's SOUPS, ACM's CSCW, ACM's CoNExt and Usenix's EuroSys among others.
His work also received a distinguished paper award in Usenix's SOUPS and Google India faculty research award in 2022.

More about his research is available here

Bio: Dr Benedikt Gierlichs is a research expert in the COSIC (Computer Security and Industrial Cryptography) research group at KU Leuven in Belgium. He works with the embedded security sub-group and leads the attacks and evaluations team. His research focuses on the (physical) security of embedded devices. He enjoys to apply cryptography to solve complex real-world challenges. He has co-authored more than 70 scientific publications in peer-reviewed, international conferences and journals. He has served on many program committees of international conferences and has co-chaired 4 of them. He is a member of the IACR, a Belgian delegate to the ISO/IEC SC27 standardization group and chairman of the CHES steering committee.

His research interest include Physical security of embedded cryptographic devices, Side Channel Analysis, Fault Analysis, Countermeasures, Secure system on chip design
More about his reserach is available here

Bio: Debdeep Mukhopadhyay is currently a Visiting Professor in the School of Computer Engineering, NYU Abu Dhabi, and is an Institute Chair Professor at the Department of CSE, IIT Kharagpur.
At IIT Kharagpur he initiated Secured Embedded Architecture Laboratory (SEAL), focusing on Hardware-Security.
He holds a PhD, MS, and a B.Tech from IIT Kharagpur.
His research interests are on the topics of Cryptographic Engineering, Micro-architectural security and Hardware-Security.
Recently he is intrigued by adversarial attacks on machine-learning, and encrypted computations, which includes homomorphic computations and searchable encryptions.

Mukhopadhyay has published more than 250 papers in peer-reviewed conferences and journals, and is in the editorial boards and program committees of several top journals and conferences.
Mukhopadhyay is the recipient of the prestigious Shanti Swarup Bhatnagar Award 2021 for Science and Technology (highest science honor in India below the age of 45) and is a Fellow of the Indian National Academy of Engineers, and Fellow of the Asia-Pacific Artificial Intelligence Association (AAIA) for contributions to Information Security.

He is also a fellow of C3iHub (Cyber Security and Cyber Security for Cyber-Physical Systems) Innovation Hub of IIT Kanpur, and has been enlisted in Asia's most outstanding researchers compiled by Asian Scientist Magazine.
He was awarded the Qualcomm Faculty Award 2022, Khosla National Award from IIT Roorkee 2021, DST Swarnajayanti Fellowship 2015-16, INSA Young Scientist award, INAE Young Engineer award, and Associateship for the Indian Academy of Sciences and is a senior member of IEEE/ACM.

Title: Foundations of Secure Multi-party Computation

Abstract: Traditionally, cryptography is used to protect data in transit from an eavesdropping adversary. With the advent of big data and large-scale computation, cryptography can offer us much more. A cryptographic tool called Secure Multi- party Computation (MPC) allows a set of mutually distrusting entities to compute a combined function on their private inputs, with the guarantee that nothing beyond the output of the computation is revealed. The current and potential impact of MPC is widespread in real-life applications where data sharing is constrained due to legal, ethical or privacy reasons.

In this tutorial, we will learn the foundations of MPC protocols. In particular, we focus on two types of standard approaches used in the design of MPC protocols: secret-sharing based and garbled-circuit based protocols.

Bio: Divya Ravi is currently an Assistant Professor in the Complex Cyber Infrastructure (CCI) Group at University of Amsterdam, Netherlands.

Previously, she was a post-doctoral researcher in the Cryptography and Security Group at Aarhus University, Denmark. she received her PhD at Indian Institute of Science (IISc), Bangalore, India where she was supervised by Dr. Arpita Patra . She completed M.E (Masters) in Computer Science from CSA, IISc and B.E (Bachelors) in Computer Science from BITS Pilani, Hyderabad Campus, India.

Her research interests primarily include Secure Multi-party Computation and Distributed Computing.

More specifically, she is interested in finding solutions to intriguing questions such as the feasibility of tasks related to secure multiparty computation (MPC) and construction of efficient distributed computing protocols under different settings of network and computational models

More about her reserach is available here

Title: HARDWARE SOLVERS OVER GF(2)

Abstract: It is well known that linear equations over any finite field can be solved using Gaussian Elimination (GE) efficiently. GE is even more efficient to implement in hardware, and there have been numerous architectures proposed for it.

Regarding higher degree equations, the hardware architecture proposed in BCC+13 uses gray code based search to solve only quadratic equations. The idea is to efficiently traverse the space of potential solutions via a graycode path, which takes much less computational load than traversing it lexicographically. But this architecture is limited to degree 2 equations and so for a while solving higher degree equation system efficiently in hardware was an open problem.

Möbius transform is a linear circuit used to compute the evaluations of a Boolean function over all points on its input domain. The operation is very useful in finding the solution of a system of polynomial equations over GF (2) for obvious reasons. However the operation, although linear, needs exponential number of logic operations (around $n \cdot 2^{n−1}$ bit xors) for an n-variable Boolean function. As such the only known hardware circuit to efficiently compute the Möbius Transform requires silicon area that is exponential in n. For Boolean functions whose algebraic degree is bound by some parameter d, recursive definitions of the Möbius Transform exist that requires only O(n^{d+1} ) space in software. However converting the mathematical definition of this space-efficient algorithm into a hardware architecture is a non-trivial task, primarily because the recursion calls notionally lead to a depth-first search in a transition graph that requires context switches at each recursion call for which straightforward mapping in hardware is difficult. In this paper we look to overcome these very challenges in an engineering sense. We propose a space efficient sequential hardware circuit for the Möbius Transform that requires only polynomial circuit area (i.e. O(n^{d+1} )) provided the algebraic degree of the Boolean function is limited to d. We show how this circuit can be used as a component to efficiently solve polynomial equations of degree at most d by using fast exhaustive search. We propose three different circuit architectures for this, each of which uses the Möbius Transform circuit as a core component. We show that asymptotically, all the solutions of a system of m polynomials in n unknowns and algebraic degree d over GF (2) can be found using a circuit of silicon area proportional to $m \cdot n^{d+1}$ and circuit depth proportional to $2 \cdot \log_2 (n - d)$.
We then introduce the architecture Polysolve4, a hardware solver that additionally aims to achieve energy efficiency. The main idea is we reduce the solution space to a small enough value by parallel application of Möbius Transform circuits over the first few equations of the system. This is done so that one can check individually whether the vectors of this reduced solution space satisfy each of the remaining equations of the system using lower power consumption. The new circuit has area also bound by $m \cdot n^{d+1}$ and has circuit depth proportional to $d \cdot log_2 n$. We also show that further optimizations wrt energy may be obtained by using depth-bound Möbius circuits that exponentially decrease run time at the cost of additional logic area and depth.

Bio: Subhadeep Banik completed his B.Tech in Electronics and Electrical Communication Engineering and M.Tech in Automation and Computer Vision from the Indian Institute of Technology at Kharagpur in 2006. He received his PhD in Computer Science from the Indian Statistical Institute, Kolkata in 2015.

He was a Post Doctoral Researcher in DTU Compute at Lyngby and at Temasek Labs, NTU Singapore. He worked as an Ambizione fellow in the LASEC group in Ecole Polytechnique Federale de Lausanne since June 2017.He is currently at USi in Lugano.

More about his research is available here